Static random access memory (SRAM) cells are typically composed of two inverters. SRAM cells have a flip-flop structure in which the input/output ports of the inverters are cross-coupled. Typically only four transistors are used to store information in the SRAM cell, however, two additional transistors can be connected thereto to select a desired cell from outside the cell. Unlike a dynamic random access memory (DRAM), an SRAM can retain static data without a refresh operation.
FIG. 1 is a circuit diagram of a conventional SRAM cell and FIG. 2 illustrates a planar view of a conventional SRAM cell, which is symmetrical along the k-k′. As illustrated in FIG. 1, the SRAM cell includes first and second access transistors AT1, and AT2, first and second pull-up transistors PT1 and PT2, and first and second driver transistors DT1, and DT2.
The first pull-up transistor PT1 and the first driver transistor DT1 compose a first inverter. Similarly, the second pull-up transistor PT2 and the second driver transistor DT2 compose a second inverter. As illustrated, the first and second inverters are crossed coupled to first and second nodes N1 and N2, respectively.
Source regions of the first and second driver transistors DT1 and DT2 are connected to a ground line voltage VSS. The source regions of the first and second pull-up transistors PT1 and PT2 are connected to a power line voltage VDD. A drain of the first access transistor AT1 is connected to a first bit line BL1. A drain of the second access transistor AT2 is connected to a second bit line BL2. Sources of the first and second access transistors AT1, and AT2 are connected to first and second nodes N1 and N2, respectively. Gate electrodes of the first and second access transistors are connected to a common word line WL.
Referring now to FIG. 2, a field oxide layer 106 is formed on the integrated circuit substrate to define first and second active regions 102a and 102b. Gate layers 115, 117a and 117b cross over the field oxide layer 106 and the active regions 102a and 102b. The gate layers 115, 117a and 117b compose a word line 115 and first and second gate electrodes 117a and 117b. The word line 115 crosses over the first active region 102a and forms gates of the first and second access transistors AT1, and AT2.
As illustrated in FIG. 2, the first gate electrode 117a is orthogonal to the first word line 115. The first gate electrode 117a crosses over the first and second active regions 102a and 102b to form gates of the first driver transistor DT1 and the first pull-up transistor PT1 and to connect the gates of the first driver transistor DT1, and the first pull-up transistor PT1. The second gate electrode 117b is parallel to the first gate electrode 117a. The second gate electrode 117b crosses over the first and second active regions 102a and 102b to form gates of the second driver transistor DT2 and the second pull-up transistor PT2 and to connect the gates of the second driver transistor DT2 and the second pull-up transistor to the PT2.
An N+ type impurity-doped region 124 is formed in the first active region 102a among the gate layers 115, 117a and 117b by implanting highly doped N+ type impurity ions. A P+ type impurity-doped region 125 is formed in the second active region 102b between the gate layers 117a and 117b by implanting highly doped P+ type impurity ions.
The N+ type impurity-doped region 124 between the first access transistor AT1 and the first driver DT1 becomes the first node N1. The first node N1 is connected to a first common connection line (not shown) through a contact CT2a. The first common connection line is connected to a drain of the first pull-up transistor PT1 through a contact CT5a and to the gates of the second driver transistor DT2 and the second pull-up transistor PT2 through a contact CT3b. 
The N+ type impurity-doped region 124 between the second access transistor AT2 and the second driver transistor DT2 becomes the second node N2. The second node N2 is connected to a second common connection line (not shown) through a contact CT2b. The second common connection line is connected to a drain of the second pull-up transistor PT2 through a contact CT5b and to the gates of the first driver transistor DT1 and the first pull-up transistor PT1 through a contact CT3a. 
Contacts CT1a and CT1b connect the drains of the first and second access transistors AT1 and AT2 to the first and second bit lines BL1 and BL2 (not shown), respectively. A contact CT4 connects the sources of the first and second pull-up transistors PT1 and PT2 to the power line voltage VDD (not shown). A contact CT6 connects the sources of the first and second driver transistors DT1 and DT2 to the ground line voltage VSS (not illustrated).
A conventional SRAM typically operates at high speeds and consumes a relatively small amount of power. However, a unit cell of a conventional SRAM may occupy a large area, which may be a problem in highly integrated devices. Furthermore, as SRAM devices become more highly integrated, a channel length of a transistor in the SRAM may be decreased as a result of an increasing leakage current. The increase in the leakage current may further result in increasing a standby current. Accordingly, it may become more difficult to provide an SRAM that consumes a relatively small amount of power. Thus, improved SRAMs may be desired.